Since Intel-based CPUs do not support NVLinks (and are unlikely to ever support them), a couple of variations are possible from two to four P100 GPUs. The four GPUs are fully connected to each other with the fourth link going to the CPU. A typical full configuration node consists of four P100 GPUs and two Power CPUs. Since the P100 only has four NVLinks, a single link from each GPU can be used to link the CPU to the GPU. The first CPU to support NVLink natively was the IBM POWER8+ which allowed the NVLink interconnect to extend to the CPU, replacing the slower PCIe link. In the most basic configuration, all four links are connected between the two GPUs for 160 GB/s GPU-GPU bandwidth in addition to the PCIe lanes connected to the CPU for accessing system DRAM. The P100 has four NVLinks, which supports up to 20 GB/s for a bidrectional bandwidth of 40 GB/s for a total aggregated bandwidth of 160 GB/s. P100 comes with its own HBM memory in addition to being able to access system memory from the CPU side. ![]() NVLink 1.0 was first introduced with the P100 GPGPU based on the Pascal microarchitecture. If this is the first transaction, the CRC assumes the prior transaction was a NULL transaction. The next packet will have the CRC done over the current header as well as the two data payload from the prior transaction. Note that since the header also incorporates the packet length, it is also gets included in the CRC check.įor example, consider a sequence of two data payload (32 bytes) flits and their accompanying header. CRC is actually calculated over the header and the previous payload, eliminating the need for a separate CRC field for the data payload. The CRC field consists of 25 bits, allowing up to 5 random bits in error for the largest packet or alternatively, for differential pair bursts it can support up to 25 sequential bit errors. ![]() A missing acknowledgment following a timeout will initiate a reply sequence, retransmitting all subsequent packets. Transmitted packets are sequenced and a positive acknowledgment is sent back to the source upon a good CRC. ![]() The receiver is responsible for keeping the data in a replay buffer. Error detection is done through the 25-bit cyclic redundancy check header field. Nvidia specifies the error rate at 1 in 1×10 12. The address extension (AE) flit is reserved for fairly static bits and is usually transmitted only bits change. The data link field includes things such as the packet length, application number tag, and acknowledge identifier. The transaction field includes the request type, address, flow control bits, and tag identifier. It comprises a 25-bit CRC field (discussed below), 83-bit transaction field, and a 20-bit data link (DL) layer field. A typical transaction has at least request and response with posted operations not necessitating a response. In bidirectional traffic, this is slightly reduced to 88.9% and 66.7% respectively.Ī packet comprises of at least a header, and optionally, an address extension (AE) flit, a byte enable (BE) flit, and up to 16 data payload flits. Each flit is 128-bit, allowing for the transfer of 256 bytes using a single header flit and 16 payload flits for a peak efficiency of 94.12% and 64 bytes using a single header flit and 4 data payload flits for an efficiency of 80% unidirectional. To ease routing, NVLink supports lane reversal and lane polarity, meaning the physical lane ordering and their polarity between the two devices may be reversed.Ī single NVLink packet ranges from a one to eighteen flits. The pairs are DC coupled an use an 85Ω differential termination with an embedded clock. ![]() A single NVLink is a bidirectional interface which comprises 8 differential pairs in each direction for a total of 32 wires. For supported microprocessors, the NVLink can eliminate PCIe entirely for all links.Īn NVLink channel is called a Brick (or an NVLink Brick). Although it's unlikely that NVLink would be implemented on an x86 system by either AMD or Intel, IBM has collaborated with Nvidia to support NVLink on their POWER microprocessors. It's worth noting that NVLink was also designed for CPU-GPU communication with higher bandwidth than PCIe. NVLink is designed to replace the inter-GPU-GPU communication from going over the PCIe lanes. Throughput could further improve through the use of a PCIe switch. Although direct GPU-GPU transfers and accesses were already possible using Nvidia's Unified Virtual Addressing over the PCIe bus, as the size of data sets continued to grow, the bus became a growing system bottleneck. Prior to the introduction of NVLink with Pascal (e.g., Kepler), multiple Nvidia's GPUs would sit on a shared PCIe bus. Announced in early 2014, NVLink was designed as an alternative solution to PCI Express with higher bandwidth and additional features (e.g., shared memory) specifically designed to be compatible with Nvidia's own GPU ISA for multi-GPU systems.
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